With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. In microelectronic packaging, a semiconductor die is bonded to a packaging substrate through a first level interconnect such as solder joints. Typically, the first level interconnect between the die and the packaging substrate is subjected to significant stress due to coefficient of thermal expansion mismatch between the die and the packaging substrate.
One way of reducing the stresses is by adding carbon nanotubes in the vertical first level interconnect stack. However, integration of carbon nanotubes in the first level interconnect is a challenge due to synthesis of carbon nanotubes at high temperatures that may cause permanent degradation to either the die or the packaging substrate.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.